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a history of microprocessing vol 23: berkeley risc​-​ii

by dsic

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1.
VLSI 05:07
2.
Lack of String Support 07:48
3.
Dribble-Back File Registers 07:28
4.
For Sherbourne & Katevenis 03:59

about

"In parallel with the design of RISC I, the present author defined a second, more ambitious micro-architecture for the same processor architecture, and sub-sequently implemented it, together with Robert Sherburne, by designing, laying-out, and debugging a second NMOS IC. This was originally called "RISC I Blue", and later on "RISC II". It was fabricated and tested in 1983. The chips are functionally correct and work very close to predicted speed. RISC Il occupies 25% less silicon area than RISC I, even though it has 75% more registers. This was made possible by reducing the number of busses that go through the register file from three to two, which led to a much more compact register cell. To avoid a resulting performance loss, an additional pipeline stage was used, as suggested by Lloyd Dickman. Overall, the circuit design and layout for RISC II was done with careful attention to performance."

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released May 1, 2022

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