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a history of microprocessing vol 24: stanford mips

by dsic

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1.
Microprocessor without Interlocked Pipeline Stages 19:21
2.
For John L. Hennessey 05:16

about

"MIPS is a new 32-bit processor designed to execute compiled code for general purpose applications. MIPS is both a streamlined (or reduced) instruction set architecture and an implementation of that
architecture as an nMOS chip. The MIPS implemctation has several goals. First, we wanted to determine whether a competitive 32-bit processor could be built using the concepts in the MIPS architecture and Mead-Conway style design. A number of benchmarks have been run on the 68000 (at 8MHz) and our MIPS simulator (assuming a clock period of 4MHz). These benchmarks have shown an average speed-up of 460% for C programs and 550% for Pascal programs using the same compiler technology for both processors. If we can build a 4MHz part, we will have succeeded in demonstrating the architecture and implementation."

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released May 10, 2022

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