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a history of microprocessing vol. 31: hp pa​-​risc ts​-​1

by dsic

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1.
Transition Lookaside Buffer 07:03
2.
9000/840 03:32
3.
HP-UX 06:16
4.
FAST TTL 04:57
5.
X and B Bus 04:58

about

The TS-1 marked the beginning of HP's PA-RISC journey, which dominated the server market for over two decades.

Technical Specs:

Architecture: PA-RISC 1.0 (32-bit)
Clock Speed: 8 MHz
Implementation: Six boards of TTL logic (Transistor-Transistor Logic)
Cache: 128 KB L1 cache (64 KB each for data and instruction)
Instruction Set: RISC (Reduced Instruction Set Computing) designed for simplicity and speed
Use Cases: Servers (HP 9000/840) and high-performance workstations

credits

released January 6, 2024

license

all rights reserved

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